CS501 VU Current Final Paper Spring July 2012

5 marks

1. The following table shows a partial summary of the ISA for the SRC. Write an assembly language program using the SRC assembly language to evaluate the
expression:

Z= (7 + 16a) – (8b – c)

Note: a, b and c are names of memory locations. Your program should not change the source operands. Do not worry about the contents of a and b. There is no
need to worry about assembler directives. Comments in your code may be helpful.
Find the bandwidth of a memory system that has a latency of 30ns, a pre charge time of 10ns and transfers 3 bytes of data per access .

2. Explain the Direct Mapping cache strategy.
3. How many platters are required for a 40GB disk if there are 1024 bytes/sector, 2048 sectors per track and 4096 tracks per platter?
3 marks

1. What do you understand by RAID 2?
2. Give an example for the logic design level, circuit level and mask level abstractions of digital design.
3. Differenciate between Spatial Locality And Temporal Locality .
4. Suppose an I/O system with a single disk gets (on average) 200 I/O requests/second. Assume that average time for a disk to service an I/O request is 4ms.
What is the utilization of the I/O system?

2 marks

1. Which term do we use to describe a “storage systems” resilience to disk failure through the use of multiple disks and by the use of data distribution and
correction techniques?
2. Differentiate between CPU register and VUsolutions Cache Memory.
3. Write one advantage and one disadvantage of cache design.
4. What is the format of a 0-address instruction set?

How many drives do you need a minimum to form RAID 0?
0
Only 1
Minimum 2
Maximum 2

CS501 Fall 2011 Final Term 16 Feb 2012

CS501 Fall 2011 Final Term Feb 2012 – VU Current Paper – 16 Feb 2012

2 Marks

How can overflow occur in floating point?
What is Packet Switching?
Difference between Eagle and modified Eagle
Why we represent sometime some numbers in sign magnitude form.

3 Marks

What is 4-address instruction set and when it use?
Difference between virtual address and physical address
Why Transaction Lockaside Buffer is used? How it is implemented inside CPU?
What is sender overhead and receiver overhead in computer networks?

5 Marks

What is difference of instruction in machine with and without Pipeline?
Convert (0.23)10 to the base 2 address.

Consider a 4 way set-associative cache with 256KB capacity and 32 byte lines
a) How many sets are there in the cache?
b) How many bits of address are required to select a set in cache?

Find the average access time of a level of memory hierarchy if the hit rate is 80%. The memory access takes 12ns on a hit and 100ns on a miss.

CS501 GDB Solution Spring 2012

Do you agree with the statement that Multi-core processor is a special kind of a multiprocessor? If yes or no state your reasons to support your answer.
Solution:

A multi-core processor is an integrated circuit (IC) to which two or more processors have been attached for enhanced performance, reduced power consumption, and more efficient simultaneous processing of multiple tasks . A dual core set-up is somewhat comparable to having multiple, separate processors installed in the same computer, but because the two processors are actually plugged into the same socket, the connection between them is faster. Ideally, a dual core processor is nearly twice as powerful as a single core processor. In practice, performance gains are said to be about fifty percent: a dual core processor is likely to be about one-and-a-half times as powerful as a single core processor.
Multi-core processing is a growing industry trend as single core processors rapidly reach the physical limits of possible complexity and speed. Companies that have produced or are working on multi-core products include AMD, ARM, Broadcom, Intel, and VIA. Both AMD and Intel have announced that they will market dual core processors by 2005. At their 2004 Fall Developer Forum Intel predicted that, excepting their Celeron line, 40% of all processors the company ships will be multi-core by the end of 2006.

CS501 assignment no 5 July 2012 Due Date: 4-7-2012

 CS501 assignment no 5 July 2012 Due Date: 4-7-2012

 IDEA SOLUTION

Intel R CoreTM i7 Processor Extreme Edition

Intel Core I7-960 [33, 40] is a 45nm technology general-purpose processor that does ”everything” well. It targets high-end desktop, server, and workstation systems. Concerning the computational power, it has 4 cores with four-way out-of-order execution model and can use up to two threads per core, thus enabling fairly good multitasking and multithreading. With a maximal frequency of 3.33GHz, it can deliver up to 55GFLOPS. The high price for large programming flexibility is paid 15 with power consumption of maximal 130W. The core architecture is standard Intel 64 architecture [37], while the microarchitecture is based on Intel Microarchitecture (Nehalem) [36]. The main architectural features (that Intel is very proud of) are the scalability (dynamical scalability and design-scalable microarchitecture) and energy/performance efficiency. Block diagram of the processor is presented in

Many levels of memory (memory hierarchy) are used to hide memory latencies. It has three levels of cache (L1- 32KB of instruction and 32KB of data cache, L2- 256KB for data and instructions, L3- 8MB) and integrated memory controller that can support memory bandwidth of 25GB/s, which is also the maximal bandwidth supported by the interconnect. The amount of supported DRAM is outstanding 24GB [40]. The communication among the cores and between the cores and DRAM is done via Intel QPI point-to-point link capable of providing 25GB/s.

CS501 Assignment # 4 Idea Solution June 2012

CS501 Assignment # 4 Idea Solution,,,,,

MIPS = Millions Instruction Per Second
Please do not for Hard Drive Case 500 instead of 250, cause in assignment hard drive speed is double 2MB/sec.
Please be aware that CPU instruction speed is not fully dependent on Perpherial Device speed, Bus speed and capacity is also occur significant roll in that senario.

For Hard Drive:

10^6 = 1 Million (10,00,000)
first calculate how many bits in 2MB = 16777216 (bits in 2 megabyte)
1048576 times data send in one second according to our bus speed 16-bit (16777216/16)

After that convert this data into Kilobyte and calculte Polled and get percentage.
But remember that our assignment senario is 100 MIPS so divide value is 100 MIPS.

Floopy Drive is also same calculation process follow, but replace accurate values.

If you have any problem feel free to contact me.
mc100204818@vu.edu.pk