CS501 assignment no 5 July 2012 Due Date: 4-7-2012

 CS501 assignment no 5 July 2012 Due Date: 4-7-2012

 IDEA SOLUTION

Intel R CoreTM i7 Processor Extreme Edition

Intel Core I7-960 [33, 40] is a 45nm technology general-purpose processor that does ”everything” well. It targets high-end desktop, server, and workstation systems. Concerning the computational power, it has 4 cores with four-way out-of-order execution model and can use up to two threads per core, thus enabling fairly good multitasking and multithreading. With a maximal frequency of 3.33GHz, it can deliver up to 55GFLOPS. The high price for large programming flexibility is paid 15 with power consumption of maximal 130W. The core architecture is standard Intel 64 architecture [37], while the microarchitecture is based on Intel Microarchitecture (Nehalem) [36]. The main architectural features (that Intel is very proud of) are the scalability (dynamical scalability and design-scalable microarchitecture) and energy/performance efficiency. Block diagram of the processor is presented in

Many levels of memory (memory hierarchy) are used to hide memory latencies. It has three levels of cache (L1- 32KB of instruction and 32KB of data cache, L2- 256KB for data and instructions, L3- 8MB) and integrated memory controller that can support memory bandwidth of 25GB/s, which is also the maximal bandwidth supported by the interconnect. The amount of supported DRAM is outstanding 24GB [40]. The communication among the cores and between the cores and DRAM is done via Intel QPI point-to-point link capable of providing 25GB/s.